The block diagram of a basic dual-comparator R-C relaxation oscillator is shown in FIG. 1. The circuit consists of three functional sub-blocks: (i) the comparators X.sub.1 and X.sub.2 for detecting the threshold voltages V.sub.TH and V.sub.TL, set by the resistive divider network including the resistors R.sub.A, R.sub.B and R.sub.C ; (ii) the timing components including the resistor R.sub.T, the capacitor C.sub.T and the resistor R.sub.D ; and (iii) an R-S latch X.sub.3 for controlling the discharge of the capacitor C.sub.T through the npn transistor Q.sub.D and the resistor R.sub.D.
Assuming that the output Q of the R-S latch X.sub.3 is at a logical low and the transistor Q.sub.D is turned off initially, the resistor R.sub.T will charge the capacitor C.sub.T towards the upper threshold voltage V.sub.TH. The upper threshold voltage V.sub.TH is set by the resistive divider as ##EQU1##
The output of the comparator X.sub.1 rises from a logical low to a logical high when the voltage across the capacitor C.sub.T crosses the upper threshold voltage V.sub.TH and the positive input of the comparator X.sub.1 becomes greater than its negative input. Once the output of the comparator X.sub.1 switches to a logical high, the input S of the R-S latch X.sub.3 will also be raised to a logical high and the output Q of the R-S latch X.sub.3 will rise from a logical low to a logical high. The transistor Q.sub.D will then turn on and saturate. If the value of the resistor R.sub.D is properly chosen, the transistor Q.sub.D and the resistor R.sub.D will discharge the voltage across the capacitor C.sub.T towards the lower threshold voltage V.sub.TL set again by the resistive divider network as ##EQU2##
As the voltage across the capacitor C.sub.T is discharged below the upper threshold voltage V.sub.TH and the positive input of the comparator X.sub.1 becomes less than the negative input, the output of the comparator X.sub.1 will drop from a logical high to a logical low. When the voltage across the timing capacitor C.sub.T falls below the lower threshold voltage V.sub.TL so that the negative input of the comparator X.sub.2 is less than the positive input, the output of the comparator X.sub.2 will rise to a logical high and the R-S latch X.sub.3 will reset. When the R-S latch X.sub.3 is reset the output Q of the R-S latch will drop to a logical low turning the transistor Q.sub.D off and ending the discharge cycle. The resistor R.sub.T will then charge the timing capacitor C.sub.T and the cycle will repeat. The timing diagram of the oscillator of FIG. 1 is shown in FIG. 2. It can be shown that the charging time T.sub.C and the discharging time T.sub.D of the timing capacitor C.sub.T are equal to ##EQU3## respectively.
Equations (3) and (4) represent the ideal charging and discharging times of the timing capacitor C.sub.T in the absence of a propagation delay time. The effect of circuit propagation delays on the oscillator waveform is illustrated in FIG. 2. The time taken to turn on the transistor Q.sub.D and discharge the capacitor C.sub.T from the instant that the voltage across the capacitor C.sub.T rises above the upper threshold voltage V.sub.TH is represented by the time period t.sub.pd1. Likewise the time period t.sub.pd2 represents the propagation delay time for the comparator X.sub.2 and the R-S latch X.sub.3 to turn off the transistor Q.sub.D from the time that the voltage of the capacitor C.sub.T crosses the lower threshold voltage V.sub.TL. The propagation time delays t.sub.pd1 and t.sub.pd2 will cause the oscillator period to deviate from its ideal value of the charging time period T.sub.C plus the discharging time period T.sub.D. Good oscillator frequency stability requires that the time periods t.sub.pd1 and t.sub.pd2 be kept to a small fraction of the total time period. Usually the comparators X.sub.1 and X.sub.2 and the R-S latch X.sub.3 are designed for fast responses and are biased with sufficient quiescent current to shorten the propagation delay time.
If the value of the resistor R.sub.D is chosen to be much lower than the value of the resistor R.sub.T, the discharging time period T.sub.D will be much shorter than the charging time period T.sub.C. Due to the higher rate of change in the timing capacitor C.sub.T voltage during discharge, the propagation delay time t.sub.pd2 of the comparator X.sub.2 causes a larger capacitor C.sub.T voltage undershoot V.sub.US than the capacitor C.sub.T voltage overshoot V.sub.OS (FIG. 2). The voltage undershoot can be defined as the difference between the voltage at the point that the capacitor C.sub.T begins charging and the lower threshold voltage V.sub.TL. Correspondingly, the voltage overshoot can be defined as the difference between the voltage at the point that the capacitor C.sub.T begins discharging and the upper threshold voltage V.sub.TH. The time t.sub.RCV2 taken for the capacitor C.sub.T voltage to recover from its undershoot is much longer than the propagation delay time t.sub.pd2 for the comparator X.sub.2 because the capacitor C.sub.T charging rate is much lower than its discharging rate. It can also be seen from FIG. 2 that the overshoot recovery time period t.sub.RCV1 is less than the propagation delay time periods t.sub.pd1 and t.sub.pd2, which are much less than the undershoot recovery time period t.sub.RCV2. Since the propagation delay time t.sub.pd2 of the comparator X.sub.2 varies with temperature and the integrated circuit fabrication process, the undershoot recovery time period t.sub.RCV2 causes by far the highest frequency instability in the type of relaxation oscillator shown in FIG. 1. In micro power circuit design, comparator quiescent current is usually kept low. However, this approach has the consequence of prolonging the propagation delay time periods t.sub.pd1 and t.sub.pd2.
What is needed is a relaxation oscillator which minimizes the undershoot recovery time period t.sub.RCV2 and therefore also minimizes the frequency instability of the circuit. What is also needed is a relaxation oscillator which minimizes the propagation delay times and consumes low power.